1. Field of the Invention
The present invention relates to memory cells and, in particular, to ultra low voltage operated static RAM (SRAM) memory cells.
2. Description of the Related Art
Computer memory cells are in wide use today. They may be used, for example, in various forms of random-access memory (RAM), in registers, and other devices. Each memory cell stores a bit of data, i.e. a binary 0 (logic low, typically V.sub.SS or ground) or 1 (logic high, typically V.sub.DD). New data may be written into the cell, and stored data may be read from the cell. In a memory array of such cells, a row of memory cells is typically used to provide storage of larger, multi-bit units of data such as bytes or words. A given row can be used to provide one word or several words. The memory array can provide a number of rows to provide multiple word storage.
Referring now to FIG. 1, there is shown a circuit diagram illustrating a prior art memory cell 100. Memory cell 100 is a conventional 6-T (six-transistor) SRAM cell comprises a flip-flop or memory element comprising inverters 101, 102, which may be implemented with two transistors each (one nmos and one pmos transistor). The flip-flop has data node D and inverse-data node DN (data-not, the inverse of D). Data node D stores a 1 or 0 corresponding to the data stored in memory cell 100.
Cell 100 comprises a data access port such as the data access port illustrated in FIG. 1, which allows a single external device or component such as a processor to write or read a bit to the cell, at a given time. The data access port can be used as a write-access port or as a read-access port. The data access port of cell 100 comprises umos access transistors 105, 106, plus three input lines for the three signals BIT, BIT, and WL (WordLine), for purposes of writing a bit to or reading a bit from memory cell 100, from or to a single external device such as a processor. The memory cells of a given column of an array of memory cells typically share the same data access ports. FIG. 2 is a block diagram of a memory cell system or array 200 employing conventional SRAM memory cells such as cell 100.
Cell 100 may be powered by a power supply voltage of, say, V.sub.DD =3V. Nmos transistors such as transistors 105, 106 have a typical threshold drop of approximately 0.6V. Due to the threshold voltage of access transistor 105, the input signal on a single input line BIT may not be strong enough to write a 1 quickly enough, or even at all. For example, if cell 100 previously stored a 0 so that data node D was 0V, and a 1 is to be written to the cell by input line BIT, then a 1 (3V) on line BIT causes node D to raise from 0V to only 2.4V, because of the voltage drop of 0.6V across transistor 105. Increasing node D to 2.4V may be too low to quickly raise the cell to a 1 state from a 0 state, because it may be slow to overcome the current 0 state of the cell.
Even worse, with even lower supply voltages such as 1.2V, node D would only be raised to 0.6V, which is insufficient to guarantee that node D is pulled high quickly enough or even at all. With smaller and smaller supply voltages, because of the voltage drop of the access transistor of the data access port, a single input line is unable, in the prior art, to override the previous 0 state to write a 1 state.
Thus, two input lines, BIT and BIT, are typically used to store the signal provided by the BIT line in a memory cell such as cell 100. To store a value in cell 100, signal WL goes high, and BIT provides the signal to be stored, while BIT provides the inverse of the BIT signal. In the case where D was is 0 from the previous memory state, and BIT carries a 1 (1.2V) to be stored in cell 100, BIT is 0V and so is node DN, because there is no voltage drop across transistor 106 when BIT is 0. A 0 or low signal at the input to inverter 102 causes inverter 102 to bring node D quickly up to 1. Thus, each write-access port requires two access transistors such as transistors 105, 106 plus four input lines carrying three input signals. For a write operation, the BIT signal is derived from the data signal provided by the processor writing into the cell. The BIT signal is provided by an inverter external to the memory cell array. The WL signal is provided by memory control logic which itself receives address information from the processor.
Similarly, the data access port may be used as a read-access port. In this case access transistors 105, 106 serve as read-access transistors. To read the state or bit of cell 100, an output line coupled to each of the BIT and BIT terminals has to be precharged. Then, the read-access transistors 105, 106 are turned on, allowing the cell to discharge one of the two precharged lines, depending on whether the cell is high or low. When a line is discharged, external circuitry can detect this and thus will be able to tell whether the memory cell 100 has a 0 or 1 stored therein.
A dynamic RAM (DRAM) type memory cell comprises a capacitor and a transistor. The capacitor tends to lose data unless it is recharged often, e.g. once every few milliseconds. This recharging tends to slow down the performance of DRAM compared to other types of RAM. A static RAM (SRAM) memory cell stores a data bit in a capacitor that does not require constant recharging to retain data. Thus, SRAM performs better than DRAM because it does not need to be constantly recharged. For example, the typical access time for an SRAM is three to four times faster than that for a DRAM. SRAM is often used for secondary caches because its speed falls somewhere between that of DRAMs and a CPU-based cache.
It is desirable to be able to operate memory cells, such as SRAM cells, at very low voltages (sometimes referred to as ultra low voltages), e.g. &lt;0.9V. Previous attempts to achieve low voltage operation SRAM cells utilize either low V.sub.t (threshold voltage) processing and/or a vers specialized sense-amp. However, the low V.sub.t design typically causes cell stability and sub-threshold leakage problems. A specialized sense-amp is typically a custom-designed circuit which is not easily transferable from one technology to another, and it normally imposes very strict operating conditions. Accordingly, it is desirable to operate SRAM cells at ultra low voltages, without using a low V.sub.t processing, with very low power dissipation, and with a read-write access time comparable to that achieved in memory cells operated at a high voltage (e.g., &gt;2.5V).